Current demands for high density and performance associated with ultra large scale integration require submicron features of about 0.25 microns and under, increased transistor and circuit speeds and improved reliability. Such demands for increased density, performance and reliability require device features with high precision and uniformity.
Conventional semiconductor devices comprise a substrate and various electrically isolated regions, called active regions, in which individual circuit components, such as transistors comprising gates and source/drain regions, are formed and interconnected. In one interconnection scheme, source/drain regions and gates of neighboring transistors are connected to one another by local interconnections to form "standard cells" which, in turn, are connected to each other locally and globally by several patterned metal layers interleaved with dielectric layers formed above and extending substantially horizontally with respect to the substrate surface. The metal layers are connected to one another and to the local interconnections by vias.
Conventional practices comprise depositing a composite three-layer metal stack comprising an upper layer of titanium nitride (TiN) or titanium--titanium nitride (Ti--TiN), an intermediate aluminum (Al) or Al alloy layer and a lower layer of titanium (Ti) or Ti--TiN, as by sputtering. A patterned photoresist mask is then formed on the metal layer defining a metal pattern and the underlying metal is etched to form the pattern of metal lines. The quality of the photoresist mask is crucial to the definition of the metal interconnect layer and, hence, to device performance. Thus, if defects are observed or detected in the mask, it must be removed and replaced with a defect free mask before etching. Conventional photoresist mask removal techniques include subjecting the wafer to oxygen plasma stripping at about 240.degree. C. to about 260.degree. C., followed by solvent cleaning. A new patterned photoresist mask is then formed on the underlying metal layer and etching is conducted to form the patterned metal lines.
After investigation, it was found that wafers which were processed by such conventional defective mask removal and replacement procedures exhibit an abnormally high defect density during the subsequent metal etch, due to the presence of residue in between the etched metal lines. The impact of stripping residue is illustrated in FIG. 1, depicting substrate 1, field oxide 2, device components 3, 4, local interconnect 5, contacts 6, insulating material 7, metal lines 8 and residue R. It is believed that residue R forms a conductive bump on insulating material 7 which causes "bridging" between adjacent metal lines 8 and, hence, short circuiting and device failure. Some residue R can be formed even if the photoresist is not replaced; however, it was found that conventional photoresist mask replacement generates a considerably greater amount of conductive residue causing a high reject rate.
There exists a need for semiconductor methodology enabling replacement of a defective photoresist mask, then subsequently etching an underlying metal layer, without encountering short circuiting between resulting metal lines due to conductive residue. There exists a particular need for such photoresist mask rework methodology in manufacturing high density devices having minimal interwiring spaces.